The present invention relates to multi-layered printed circuit boards and to the testing of vias therein.
A via is a vertical plated hole, usually drilled, in a multi-layer printed circuit board (PCB), used to provide electrical connection between two or more layers in the PCB. If the via connects two or more layers within the PCB, not including either outer layer, it is called a buried via. If the via connects two or more layers to include one of the outer layers, it is called a blind via (blind top via or blind bottom via). If a via connects all layers, it is called a through via. The term xe2x80x9cviaxe2x80x9d as employed herein, will be used to describe all types of vias, as described above.
The via, as an essential element of any high-speed PCB, has its own associated electrical parasitics including inductance and capacitance. Parasitics are inherent properties of a real component that cause its operation to deviate from that of an ideal component. Via parasitics directly affect system specifications and play an important role in the degradation of high-speed signals, especially signals at multi-Gigabit rates. In order to investigate overall system performance, via parasitics need to be extracted and used in system analyses.
Testing and extracting information regarding these parasitics have become indispensable tasks in designing multi-Gigabit high-speed fiber optic products. Engineers have treated these tasks as the bottleneck of Gigabit signal flow on a PCB. Without a thorough understanding and quantitative knowledge of the high-speed via, it would be difficult to successfully design the next generation of fiber optic products.
Prior art methods for via parasitics extraction may be divided into three categories: Experimental Methods; Simulation Methods; and Theoretical Methods.
Experimental Methods utilize a Time Domain Reflectometer (TDR) scope with built-in extraction capabilities. The built-in TDR extraction capability has, however, been proved to be inaccurate when the via structure being considered is of the type to be applied to Gigabit applications.
Simulation Methods utilize a 3-dimensional field solver to construct the via structure and extract the parasitics which then have to be verified by TDR measurement. The simulation process is thus lengthy and prone to produce unreliable results. Experimental verification is also needed to assess the results.
Theoretical Methods utilize 3-D electromagnetic (EM) theory, in order to solve for a particular via structure, which has an analytic solution. Such theoretical solutions, however, cannot be applied to the practical via structures that are used for Gigabit applications.
A further method has been disclosed in David J. Dascher, xe2x80x9cMeasuring Parasitic Capacitance and Inductance Using TDRxe2x80x9d, Hewlett-Packard Journal, April 1996, which attempts to overcome some of the drawbacks of these prior art methods. Dascher discloses a method of using TDR to measure any discontinuity in transmission line systems very accurately. However, the method in Dascher has some limitations associated therewith. For instance, for the Dascher method to be accurate: (1) the via structure being considered must be either primarily capacitive or primarily inductive, since the structure is to be modeled by a single element; and (2) the two transmission lines connected to the via being considered must be lossless. These restrictions exclude situations that are commonly encountered with vias used in emerging Gigabit applications. Moreover, in light of further investigation, some of the conclusions that were reached in the Dascher publication appear to be incorrect, which further limits the application of the method disclosed therein.
Therefore, there is a need for a method of testing via parasitics, and a method of extracting such information, which will overcome at least one of the drawbacks of the prior art.
The method of the present invention is a unique test and extraction process that utilizes a TDR measurement and processes the output data therefrom externally at a computing means, such as a computer running a suitable computer program. The testing aspect involves obtaining a TDR module waveform and obtaining a text file with output data, whereas the extraction aspect involves analysis of the data in the text file. This method can be used directly to ascertain a Gigabit via structure without the limitations that are imposed by the conventional methods discussed above. The invented method has been theoretically proven to be highly accurate. The speed of the test and extraction process is practically much faster than any of the existing methods. One main advantage is the method""s direct applicability to high-speed Gigabit fiber optic products.
According to an aspect of the present invention, there is provided a method of extracting via parasitics comprising the steps of: measuring, at a measuring means, a measured time domain reflectometer (TDR) waveform characterizing said via; computing, at a computing means, an analytic TDR waveform characterizing said via; comparing, at a comparing means, said measured TDR waveform and said analytic TDR waveform and outputting a comparison result; and extracting via parasitics from said comparison result.
According to another aspect of the present invention, there is provided an apparatus for extracting via parasitics comprising: measuring means for obtaining a time domain reflectometer (TDR) waveform characterizing said via; computing means for computing an analytic TDR waveform characterizing said via; comparing means for comparing said measured TDR waveform and said analytic TDR waveform and outputting a comparison result; and extracting means for extracting via parasitics from said comparison result.
According to a further aspect of the present invention, there is provided a method of designing a via according to an embodiment of the present invention comprises the steps of: a) computing, at a computing means, a first time domain reflectometer (TDR) waveform of a proposed via design, said first TDR waveform being obtained by analytic or numerical method calculations; b) comparing, at a comparing means, said first TDR waveform with a second TDR waveform having desired characteristics for said via and outputting a comparison result; c) verifying whether a variation between said first TDR waveform and said second TDR waveform is outside a defined tolerance; d) if necessary, repeating steps a) and b) until step c) produces a variation that is within said defined tolerance; and e) extracting via parasitics from said comparison result in order to design the via therefrom.
The method of the present invention is advantageous in that it is accurate and applicable to Gigabit via structures, a feature that was not present with prior art Experimental Methods. The method of the present invention, while remaining accurate, is able to produce results much faster than prior art Simulation Methods. In comparison with Theoretical Methods, the method of the present invention can be applied to practical via structures that are used for Gigabit applications.
The method of the present invention is also an improvement over the method in the Dascher publication in that it is applicable to via structures with both capacitive and inductive effects, a situation which is commonly encountered in Gigabit applications nowadays.
Although the method of the present invention is most effective for multi-Gigabit applications, such as OC-768 (2.5 Gb/s) or its next generation, since transmission lines used in such applications always have losses, the method is still effective for other applications, such as OC-192 (625 Mb/s) applications where losses must be considered.
Methods according to the present invention may be applied to any degree of complexity of the practical via structure scheme, including the presence of other nearby ground/signal vias as well as any non-trivial interconnects with sufficient efficiency and accuracy. Additionally, the results of the method of the present invention can be flexibly adapted to circuit requirements according to the physical characteristics of the Gigabit board. This flexible adaptation is a consequence of the fact that obtaining the TDR waveform automatically includes all complex factors associated with the circuit or the board, since both inductive and capacitive characteristics are considered. As such, the model does not need to be changed depending upon the complexity of the board itself, and it is not necessary to know the details of all the complex factors associated therewith in order to extract accurate via parasitics.